IBM Increases Chip Memory Size

When IBM rolls out its first 45-nanometer processors in 2008, the company’s customers, in addition to getting a much smaller and more powerful chip, can now expect increased performance in memory as well.

At the International Solid State Circuits Conference in San Francisco on Feb. 14, the company’s engineers plan on introducing a paper that shows the company’s efforts in producing an embedded DRAM (dynamic RAM) memory within a 45-nanometer chip.

This type of memory, which was developed using IBM’s SIO (Silicon-on Insulator), is three times denser than conventional SRAM (static RAM) chip memory and can offer users twice the performance of a conventional chip, said Subramanian Iyer, director of the IBM’s 45nm development.

In general, chip makers such as IBM and Intel, of Santa Clara, Calif., use SRAM to test out the new manufacturing process of chips. In this case, IBM’s engineers decided to develop process with the much denser DRAM to increase the memory or cache on the chip without producing a chip that is so large that it becomes unmanageable.

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By increasing the size of the cache and allowing more data to flow through the core, the engineers have allowed the chip to perform much faster.

“Most chips today are cache-starved,” Iyer said in an interview in advance of the show. “The result is that we are not realizing the amount of performance a processor could have. The problem then has been if you increase the size of the memory, you have to increase the size of the chip. What we are presenting today circumvents those problems and optimizes the memory, speed and a performance of the chip.”

Iyer, who has been working on this particular problem of memory and chip size for more than 10 years, said engineers were first able to solve this problem when the company created its 65nm manufacturing process. The first chips to be built using the 65-nanometer processor will be the Power6 processor, which will be released later in 2007.

However, this denser memory will first be made available when the company rolls out its 45-nanometer chips in 2008.

For practical purposes, Iyer said a chip with this type of memory could find a home in high-performance computing, storage, servers and gaming.

“I think that it’s a major breakthrough,” said David Lammers, an analyst with VLSI Research, also in Santa Clara. “This is not just a research paper. They want to use this with their high-end Unix server line [System p] and with their flagship Power processors. If they were just talking about embedded DRAM it would be news worthy, but the fact that this will enter the commercial marketplace is what really gives it some importance.”

In creating more memory on the processor, Lammers said IBM, of Armonk, N.Y., seems to have overcome two distinct problems. The first is cost, since adding more mask layers onto the chip will increase the cost to manufacture the processor.

The second was increasing the speed DRAM to make it more in line with SRAM. According to IBM, the random cycle time for this new chip will be 2 nanoseconds, while the latency will be 1.5 nanoseconds. Those configurations are in line with chips that use SRAM, Lammers said.

The biggest improvement, Lammers said, was IBM’s ability to reduce the amount of cache misses, which allows the processor to gather more instructions and data faster by using the cache on the die.

IBM has used this type of dense DRAM memory before, most notably in its Blue Gene supercomputer models.

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Iyer said this type of memory development can be used in single-core processors as well as multicore processors.

IBM has not been the only the company to use the ISSCC to launch a major processor initiative. On Feb. 11, just before the conference started, Intel announced that it had developed a processor that had up to 80 cores on a single piece of silicon.

In addition, Advanced Micro Devices, of Sunnyvale, Calif., announced new power-saving technology that it will incorporate in its quad-core Opteron processor, called Barcelona, which will be released later in 2007.

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